/*
 * SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_pcie3.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_
#define _NTHW_FPGA_REG_DEFS_PCIE3_

/* PCIE3 */
#define NTHW_MOD_PCIE3 (0xfbc48c18UL)
#define PCIE3_BUILD_SEED (0x7a6457c5UL)
#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL)
#define PCIE3_BUILD_TIME (0x51772c86UL)
#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL)
#define PCIE3_CONFIG (0xe7ef0d51UL)
#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL)
#define PCIE3_CONFIG_MAX_READ (0x2943f801UL)
#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL)
#define PCIE3_CONTROL (0x935935d4UL)
#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL)
#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL)
#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL)
#define PCIE3_CORESPEED (0x5cbe0925UL)
#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL)
#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL)
#define PCIE3_DRP_COMMON (0xffd331a2UL)
#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL)
#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL)
#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL)
#define PCIE3_DRP_COMMON_WR (0xbe76449eUL)
#define PCIE3_DRP_DATE (0xeaae0e97UL)
#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL)
#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL)
#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL)
#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL)
#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL)
#define PCIE3_INT_CLR (0xcde216faUL)
#define PCIE3_INT_CLR_AVR (0x1982c8eUL)
#define PCIE3_INT_CLR_FHM (0x5d9e0821UL)
#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL)
#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL)
#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL)
#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL)
#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL)
#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL)
#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL)
#define PCIE3_INT_CLR_INT_15 (0xbda934afUL)
#define PCIE3_INT_CLR_INT_16 (0x24a06515UL)
#define PCIE3_INT_CLR_INT_17 (0x53a75583UL)
#define PCIE3_INT_CLR_INT_18 (0xc3184812UL)
#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL)
#define PCIE3_INT_CLR_INT_2 (0x82a59259UL)
#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL)
#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL)
#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL)
#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL)
#define PCIE3_INT_CLR_INT_24 (0xe18357faUL)
#define PCIE3_INT_CLR_INT_25 (0x9684676cUL)
#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL)
#define PCIE3_INT_CLR_INT_27 (0x788a0640UL)
#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL)
#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL)
#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL)
#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL)
#define PCIE3_INT_CLR_INT_31 (0x88f29234UL)
#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL)
#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL)
#define PCIE3_INT_CLR_INT_6 (0x85c85640UL)
#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL)
#define PCIE3_INT_CLR_INT_8 (0x62707b47UL)
#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL)
#define PCIE3_INT_CLR_PORT (0x4f57e46eUL)
#define PCIE3_INT_CLR_PPS (0x3d2172d9UL)
#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL)
#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL)
#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL)
#define PCIE3_INT_CLR_STA (0xa8b278ccUL)
#define PCIE3_INT_CLR_TIMER (0x696afaafUL)
#define PCIE3_INT_FORC (0x55ea48d8UL)
#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL)
#define PCIE3_INT_FORC_FHM (0x78afd50UL)
#define PCIE3_INT_FORC_INT_0 (0x9758e745UL)
#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL)
#define PCIE3_INT_FORC_INT_10 (0xebe10398UL)
#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL)
#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL)
#define PCIE3_INT_FORC_INT_13 (0x72e85222UL)
#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL)
#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL)
#define PCIE3_INT_FORC_INT_16 (0x282a6adUL)
#define PCIE3_INT_FORC_INT_17 (0x7585963bUL)
#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL)
#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL)
#define PCIE3_INT_FORC_INT_2 (0x79568669UL)
#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL)
#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL)
#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL)
#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL)
#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL)
#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL)
#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL)
#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL)
#define PCIE3_INT_FORC_INT_28 (0xce17d869UL)
#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL)
#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL)
#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL)
#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL)
#define PCIE3_INT_FORC_INT_4 (0x9035235cUL)
#define PCIE3_INT_FORC_INT_5 (0xe73213caUL)
#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL)
#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL)
#define PCIE3_INT_FORC_INT_8 (0x99836f77UL)
#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL)
#define PCIE3_INT_FORC_PORT (0x680fb131UL)
#define PCIE3_INT_FORC_PPS (0x673587a8UL)
#define PCIE3_INT_FORC_QSPI (0x94bf821bUL)
#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL)
#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL)
#define PCIE3_INT_FORC_STA (0xf2a68dbdUL)
#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL)
#define PCIE3_INT_MASK (0x9fb55ba0UL)
#define PCIE3_INT_MASK_AVR (0xadf52690UL)
#define PCIE3_INT_MASK_FHM (0xf1f3023fUL)
#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL)
#define PCIE3_INT_MASK_IIC1 (0xf2696667UL)
#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL)
#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL)
#define PCIE3_INT_MASK_IIC4 (0x820392e8UL)
#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL)
#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL)
#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL)
#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL)
#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL)
#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL)
#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL)
#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL)
#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL)
#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL)
#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL)
#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL)
#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL)
#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL)
#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL)
#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL)
#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL)
#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL)
#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL)
#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL)
#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL)
#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL)
#define PCIE3_INT_MASK_INT_28 (0x37616068UL)
#define PCIE3_INT_MASK_INT_29 (0x406650feUL)
#define PCIE3_INT_MASK_INT_3 (0xc136d863UL)
#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL)
#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL)
#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL)
#define PCIE3_INT_MASK_INT_5 (0x28557d56UL)
#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL)
#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL)
#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL)
#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL)
#define PCIE3_INT_MASK_PORT (0xb5f4b407UL)
#define PCIE3_INT_MASK_PPS (0x914c78c7UL)
#define PCIE3_INT_MASK_QSPI (0x4944872dUL)
#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL)
#define PCIE3_INT_MASK_SPIS (0x8769a19dUL)
#define PCIE3_INT_MASK_STA (0x4df72d2UL)
#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL)
#define PCIE3_LAT_CTRL (0x5c509767UL)
#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL)
#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL)
#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL)
#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL)
#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL)
#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL)
#define PCIE3_LAT_MAX (0x316931d1UL)
#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL)
#define PCIE3_LAT_RAMADR (0x745612a7UL)
#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL)
#define PCIE3_LAT_RAMDATA (0xfc506b8dUL)
#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL)
#define PCIE3_LINK_STATUS (0xab303a44UL)
#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL)
#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL)
#define PCIE3_MARKADR_LSB (0xbf66115UL)
#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL)
#define PCIE3_MARKADR_MSB (0xa340b22UL)
#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL)
#define PCIE3_PB_INTERVAL (0x6d0029bfUL)
#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL)
#define PCIE3_PB_MAX_RD (0x14d4cfd0UL)
#define PCIE3_PB_MAX_RD_PB (0xafae2778UL)
#define PCIE3_PB_MAX_WR (0x9d778ec4UL)
#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL)
#define PCIE3_PCIE_CTRL (0x6a657a79UL)
#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL)
#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL)
#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL)
#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL)
#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL)
#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL)
#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL)
#define PCIE3_PCI_TEST0 (0x9035b95dUL)
#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL)
#define PCIE3_PCI_TEST1 (0xe73289cbUL)
#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL)
#define PCIE3_PCI_TEST2 (0x7e3bd871UL)
#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL)
#define PCIE3_PCI_TEST3 (0x93ce8e7UL)
#define PCIE3_PCI_TEST3_DATA (0x777d7216UL)
#define PCIE3_PROD_ID_EX (0x8611a98cUL)
#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL)
#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL)
#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL)
#define PCIE3_PROD_ID_LSB (0x427df3d7UL)
#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL)
#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL)
#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL)
#define PCIE3_PROD_ID_MSB (0x43bf99e0UL)
#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL)
#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL)
#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL)
#define PCIE3_RESET_CTRL (0xcc9a6c8bUL)
#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL)
#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL)
#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL)
#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL)
#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL)
#define PCIE3_SAMPLE_TIME (0x6c2ab747UL)
#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL)
#define PCIE3_STATUS (0x48654731UL)
#define PCIE3_STATUS_RD_ERR (0x153789c6UL)
#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL)
#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL)
#define PCIE3_STATUS0 (0xa54dba5cUL)
#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL)
#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL)
#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL)
#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL)
#define PCIE3_STATUS0_UR_FMT (0x5724146cUL)
#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL)
#define PCIE3_STATUS0_UR_REG (0x6cd416UL)
#define PCIE3_STAT_CTRL (0xdef3e1d7UL)
#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL)
#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL)
#define PCIE3_STAT_REFCLK (0xa4423dd2UL)
#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL)
#define PCIE3_STAT_RQ_RDY (0x3ab72682UL)
#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL)
#define PCIE3_STAT_RQ_VLD (0x9661688fUL)
#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL)
#define PCIE3_STAT_RX (0xf2a8e7a1UL)
#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL)
#define PCIE3_STAT_TX (0xa4f24027UL)
#define PCIE3_STAT_TX_COUNTER (0x80908563UL)
#define PCIE3_TEST0 (0xa0e404f1UL)
#define PCIE3_TEST0_DATA (0xf82b8d9cUL)
#define PCIE3_TEST1 (0xd7e33467UL)
#define PCIE3_TEST1_DATA (0x33775e39UL)
#define PCIE3_TEST2_DATA (0x7151e5e8UL)
#define PCIE3_TEST3_DATA (0xba0d364dUL)
#define PCIE3_UUID0 (0x96ee4e29UL)
#define PCIE3_UUID0_UUID0 (0x459d36b3UL)
#define PCIE3_UUID1 (0xe1e97ebfUL)
#define PCIE3_UUID1_UUID1 (0x94ed0d91UL)
#define PCIE3_UUID2 (0x78e02f05UL)
#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL)
#define PCIE3_UUID3 (0xfe71f93UL)
#define PCIE3_UUID3_UUID3 (0xed7c7d94UL)

#endif	/* _NTHW_FPGA_REG_DEFS_PCIE3_ */
